1. Field of the Invention
The present invention relates to a semiconductor interface circuit, and relates more specifically to an input/output circuit, commonly known as a voltage tolerant circuit, to which a voltage potential that is different from and higher than the potential of the internal power supply can be applied.
2. Description of the Related Art
Semiconductor integrated circuit (IC) technologies have developed in recent years to the point where a complete system can be manufactured in a single IC device. These single-chip system ICs typically have a transistor count exceeding several million gates with more than 500 pins for IC mounting, and combine logic, memory, CPU, analog cell, and other components that heretofore were provided on separate chips.
Semiconductor process technologies have also developed from so-called submicron level processes with line widths on the order of 0.8 .mu.m and 0.65 .mu.m, to so-called deep submicron level processes with line widths of 0.35 .mu.m and 0.25 .mu.m in response to demand for higher integration, speed, and lower power consumption. Numerous manufacturers are also currently developing processes achieving line widths of 0.18 .mu.m, 0.15 .mu.m and 0.13 .mu.m.
As process resolution has thus increased and line widths have decreased, gate insulator film thickness has also decreased. This enables IC devices to operate at higher clock rates, but has also lowered the voltage strength of the gate insulator film. More specifically, it is not possible to assure product quality at the 5-V supply voltage that is common with typical conventional ICs. Furthermore, because lowering the supply voltage is the most effective method of lowering power consumption, the typical IC supply voltage has been reduced from 5 V with submicron process devices to 3.3 V with deep submicron process devices.
This has made it necessary to use an interface capable of handling both 5 V and 3.3 V because not all peripheral components have been changed to operate at 3.3 V. Consider, for example, a PCI card or SCSI card for personal computer use. While the IC itself operates at only 3.3 V, other cards connected to the bus to which the PCI card or SCSI card is connected may operate at 3.3 V or 5 V. This requires an interface circuit that prevents problems from occurring whether a 3.3 V or 5 V signal is applied to an IC operating at 3.3 V.
Further, operation at 3.3 V cannot be assured with 0.25 .mu.m process devices, and the operating voltage must be further lowered to 2.5 V, 2 V, or even lower.
Some of the problems that can occur when 5 V is applied to a 3.3-V IC in a conventional input/output interface circuit are described next with reference to FIGS. 1a and 1b.
FIG. 1a is a section view of the driver part of an input/output (I/O) circuit, and FIG. 1b is an equivalent circuit diagram. A diode 102 is formed between the N-well 103 substrate and the drain of p-channel transistor 101 formed above the N-well 103. A diode 107 is likewise formed between the P-well 108 substrate and n-channel transistor 106 formed above the P-well 108. These diodes 102 and 107 are inevitably formed as a parasitic diode by-product of this transistor design; it is not possible to build the transistors without also forming these diodes 102 and 107.
The source of p-channel transistor 101 and N-well 103 are connected to power source VDD 104, and the source of n-channel transistor 106 and P-well 108 are connected to ground source VSS 109. As a result, diode 102 is formed between pad 105 and VDD 104, and diode 107 is formed between pad 105 and VSS 109. An equivalent circuit is shown in FIG. 1b.
When the I/O circuit is in an input mode, the gate of p-channel transistor 101 is driven to the VDD potential and the gate of n-channel transistor 106 to the VSS potential, thereby turning the transistors off. This prevents shorting the signal applied to the pad 105. However, when a signal exceeding VDD is applied to the pad 105, the pad 105 and VDD are shorted through the diode 102. That is, when 5 V is applied to a 3.3-V IC, the 5 V signal shorts the 3.3 V supply, resulting in IC operating errors and, in the worst case, in total IC failure.
A pull-up resistor between the pad and VDD and connected to the p-channel transistor results in the same problem. That is, various functional circuits of various types are connected to the same bus, and a pull-down or pull-up resistor must be provided to prevent bus floating. However, in a tolerant circuit, that is, a circuit to which an input may be applied from an external power source that is higher than the internal supply of the circuit, a pull-up resistor cannot be provided for the above-noted reason, and only circuits using a pull-down resistor have been achievable.
To resolve primarily the above-noted current leakage problem, U.S. Pat. No. 5,151,619 (Japan Examined Patent Application Publication (kokoku) H7-118644), U.S. Pat. No. 4,782,250 (kokoku H7-79232), and U.S. Pat. No. 5,721,508 teach a design in which a number of p-channel transistors in the I/O circuit are formed in a floating N-well; U.S. Pat. No. 5,144,165 (Japanese Patent No. 2547491, and U.S. Pat. No. 4,963,766 (Japan Unexamined Patent Application Publication (kokai) H3-116316) teach a design having a number of p-channel transistors forming the I/O circuit (transmission gate circuit) formed on a N-well connected to a 5-V source; and U.S. Pat. No. 5,512,844 (kokai H8-32434), U.S. Pat. No. 5,546,020 (kokai H8-8715), and U.S. Pat. No. 5,576,635 teach a design using a passgate circuit for preventing current leaks.
A problem that the related art does not resolve, however, is the current leaks that cannot be prevented under all conceivable input states and output states, that is, under all possible voltage transition states that might occur during signal input and output, in a so-called voltage tolerant interface circuit intending to accommodate inputs from both an internal source and a voltage source higher than the internal voltage source of the voltage tolerant circuit.
A further problem unresolved by the related art is the inability to achieve a voltage tolerant interface circuit having a pull-up resistance formed with a p-channel transistor.